1. Field of the Invention
The present invention relates to semiconductor switches built in an IC chip, and more particularly, to a semiconductor switch for use with high frequency signals.
2. Description of the Related Art
Various types of semiconductor switches are used as elements for switching on and off high frequency signals. Field effect transistors (hereinafter, simply referred to as “FETs”) are widely used as such semiconductor switches.
When FETs are used as switching elements, normally, the state between a drain terminal and a source terminal is switched between a conducting state and a non-conducting state by using the drain terminal and the source terminal as switch terminals and by applying control signals to a gate terminal. In other words, applying a control voltage to the gate terminal that exceeds a threshold voltage Vth, which is required for generating a channel between the drain terminal and the source terminal, allows conduction between the drain terminal and the source terminal, and thus turns on (that is, short-circuits) the switch. Also, reducing the control voltage to lower than the threshold voltage Vth to the gate terminal disconnects (that is, isolates) the drain terminal from the source terminal, and thus turns off (that is, opens) the switch.
When such an FET is provided in an IC, the control voltage must be externally applied to the gate terminal. Thus, an electrode pad is arranged on the surface of the IC chip and a wiring pattern for connecting the electrode pad to the gate terminal of the FET is arranged in the IC.
When FETs are used as switching elements, high frequency signals are always applied to the drain terminal and the source terminal, irrespective of whether the FETs are turned on or turned off. Accordingly, because of the characteristics of high frequency signals, high frequency signals are induced in the gate terminal, to which the high frequency signals are not directly applied. This phenomenon increases in accordance with an increase in the level of high frequency signals.
The high frequency signals induced in the gate terminal are transferred, via the wiring pattern and the electrode pad, to a voltage source (signal source) that supplies the control voltage to the gate terminal. The high frequency signals transferred to the voltage source have adverse influences upon other elements and circuits driven by the voltage supplied from the voltage source.
A high-frequency switching circuit shown in FIGS. 4A and 4B is suggested as a known high-frequency switching circuit using an FET that solves the problems described above.
FIG. 4A is a schematic diagram showing the structure of a known single-pole dual-throw (SPDT) high-frequency switching circuit. FIG. 4B is an equivalent circuit diagram of the known SPDT high-frequency switching circuit.
Referring to FIGS. 4A and 4B, reference numerals 1a to 1d denote FETs, reference numerals 2a and 2b denote electrode pads for applying a control voltage, reference numerals 3a to 3d denote gate wiring patterns, reference numerals 4a and 4b denote source input/output electrodes, reference numerals 5a and 5b denote drain input/output electrodes, and reference numerals 11a to 11d denote resistors. Also, reference symbol G represents a gate terminal of each of the FETs, reference symbol D represents a drain terminal of each of the FETs, and reference symbol S represents a source terminal of each of the FETs. For example, in a case where the source input/output electrode 4b is grounded and where the source input/output electrode 4a and the drain input/output electrode 5a or the drain input/output electrode 5b function as input and output terminals, such a circuit operates as an SPDT switch. Also, in such a circuit, the resistors 11a to 11d are provided on portions of the wiring patterns near the gate terminals G of the FETs 1a to 1d, respectively.
With this arrangement, an unnecessary high frequency signal induced in one or more of the gate terminals G is attenuated by the resistors 11a to 11d, and the high frequency signal is thus inhibited from being transferred to the voltage source via the electrode pads 2a and 2b. (For example, refer to Japanese Patent No. 3284015.)
However, an increase in the number of FETs provided in an IC due to an increase in the density of the IC may necessitate a long distance between a gate terminal and an electrode pad in terms of design. In other words, the length of a wiring pattern (hereinafter, referred to as a “gate wiring pattern”) between the gate terminal and the electrode pad increases. The increase in the length of the gate wiring pattern causes the gate wiring pattern to be more susceptible to high frequency signals from the outside. In other words, a high frequency signal in another circuit that should not be transferred is inevitably induced in the gate wiring pattern. In particular, when circuit elements in an IC are close to each other due to an increase in the density, the gate wiring pattern of an FET may be arranged near the source terminal and the drain terminal of another FET (shown by Part A and Part B in FIG. 4A) and near a wiring pattern connected in the source terminal or the drain terminal. In such a case, high frequency signals are likely to be induced to the gate wiring pattern, as described above.
In such a case, even if a resistor is provided in a portion of the gate wiring pattern near the gate terminal, as in the known high-frequency switching circuit described above, a high frequency signal is induced and transferred to the gate wiring pattern between the resistor and the electrode pad. Thus, the adverse influence upon a voltage source connected to the electrode pad and upon an element and a circuit driven by the voltage supplied from the voltage source cannot be avoided. Also, in contrast, if a resistor were connected in series with only a portion of the gate wiring pattern near the electrode pad, a high frequency signal induced in the gate wiring pattern would be applied to the gate terminal without being attenuated. Thus, stable operation of the FETs could not be achieved.
Furthermore, due to the induction of the high frequency signal in the gate wiring pattern, the high frequency signal is superimposed on control voltage signals applied to the gate terminals of the FETs. Thus, a resistor connected in series near the gate terminal cannot inhibit the change of the control voltage signal due to the high frequency signal. This adversely affects the frequency characteristics of insertion loss and isolation of the FETs. FIG. 5 is a frequency characteristic diagram showing the insertion loss in the high-frequency switching circuit shown in FIG. 4. As shown in FIG. 5, in the known high-frequency switching circuit, a ripple (see the arrow in FIG. 5) appears in a particular frequency range. In other words, the insertion loss and the isolation at a particular frequency are deteriorated. Since this frequency depends in part on the design of the mounting board of the IC, the frequency at which the ripple appears may be equal to the frequency used for the switching circuit, depending on the design details of the mounting board.